Cheap FOCer! (VESC compatible 4.12 redesign)

At the switch nodes(phases) on every rising edge. So this is happening at 15kHz on each phase when the FOC frequency is at 30kHz. The spike is also seen on the voltage supply.

11 Likes

@shaman If I could upvote your last three posts a thousand times, I’d have done it

7 Likes

I appreciate that @b264 :slight_smile:

5 Likes

That’s interesting… Like a pill to give me a 45 point IQ bump is interesting. What I’m trying to say is FUCK YEAH! Keep doing what ya doing.

5 Likes

Will do! :smile:

2 Likes

Inductive spiking happens when a closed circuit(with an inductor) is suddenly opened. This is not what’s happening right? You are seeing the spike at the start of a rising edge. Hmm.

2 Likes

I have probably mentioned this before, but how are you making this measurement? If you are using your scope probe with the GND clip attached, it will not work. You will just read the inductive coupling to the scope.

2 Likes

Wouldn’t that show the opposite spikes, though?

1 Like

I don’t know exactly what you mean, and I don’t know exactly what OP is measuring. My general word of warning regards trying to measure fast rising edges when there are high speed gates and big currents floating around. Everyone who has not worked with this kind of stuff before fails to make this measurement correctly and often end up chasing transients that don’t exist for months.

Maybe you know, but is OP measuring Vgs of the FETs? Or maybe phase to ground? The fact that they mention that this spike is also on the power rail, tells me there is a very good chance it is not real.

2 Likes

And how to do it right?

1 Like

extremely small probe loop area by either making custom scope probe leads and soldering them to the board, OR worst case using the spring tips instead of the alligator leads. Even the spring tips will be dodgy at these switching currents. Connect alligator GND to probe tip to see the induced currents to see how bad it is.

OP might have a really good measurement setup, worth checking though to not waste time chasing your tail.

8 Likes

I’m using an active probe with low-noise, low-inductance measurement techniques. See figure 6 of this document

No sir. It’s very real.

I encourage all who question this to read this document and the document I linked before. Parasitic induction IS responsible. This ringing is a common occurrence in any application involving H bridges such as DC/DC converters and motor controllers.

4 Likes

From the TI document:

A number of methods have been widely used to minimize the switch node ringing. These methods are listed as follows:

  1. Careful PCB layout to minimize the parasitic loop inductance in circuit [1].
  2. Gate resistor/ Bootstrap resistor to slow down the turn-on of the control FET.
  3. RC snubber circuit to attenuate the ringing.
  4. Common Source inductance to slow down the turn on of the control FET.

My current prototype has non-ideal layout of the high-current traces causing excessive parasitic inductance. This is what I get for using the cheap Chinese motor controllers as a reference for my layout…

I know there’s a lot of EE concepts I’m throwing around. It’s not trivial to understand and it takes a bit of reading to wrap you’re head around it all. I’ll be on vacation but I can do my best to answer questions anyone has about all of this.

8 Likes

Would be great if you can share the pcb layout or at least a image of the layout where you think the problem comes from.

1 Like

IMG_20190111_175620

The bottom board is the underside. There you can see two large exposed traces that run parallel to each other with the switch nodes in between. The trace closest to the edge is positive and the other is negative. Having them spaced apart like this causes a large ground loop that causes parasitic inductance

The new layout has the positive trace directly over the ground trace by the edge of the board. This reduces the loop area and therefore the parasitic inductance.

I can’t provide screen shots of the PCB layers right now as I don’t have my laptop with Altium with me right now.

8 Likes

http://www.tij.co.jp/jp/lit/ds/symlink/csd18535kcs.pdf

So I found a nice bit of information concerning how MOSFETs behave when they encounter voltage spikes above their rated max Vds. They essentially behave like a zener diode and clamp from drain to source. This event is called Avalanche. The MOSFET can handle the avalanche event for a small amount of time which is specified in the datasheet. Figure 11 in the datasheet I linked shows the avalanche characteristics of the FETs I’m using in my prototype.

The high voltage spike I’m seeing and that I’ve been battling only lasts for 100 nano-seconds. The avalanche rating suggests the MOSFET can handle this just fine even if the spike is 60V or above. I’m still seeking to squash this spike but it may not be a show stopper if I can’t squash it completely.

I don’t trust the DRV to tolerate 60V for any amount of time so I’m going to try an age old technique to try and protect it. A good old fashioned RC filter on the supply to the DRV should squash these fast spikes. This will involve a resistor in series with the power line to the DRV and will dissipate a small amount of power. Using a 4.7ohm resistor will cause only 23mW to be dissipated, assuming a supply current of 70mA, which is nothing compared to 250W+ being used by the motor.

4 Likes

Do you see the spikes when you have a battery connected or just the lab supply. I believe battery will mitigate the effects.

2 Likes

I had the same thought too and switched to a battery a while back. Unfortunately it didn’t make a difference.

1 Like

TEK0005 Ringing on furthest switch node

TEK0007 Ringing on furthest switch node after adding 4.7uF electrolytic cap by each FET’s drain pin

TEK0009 Ringing on furthest switch node after adding 4.7uF electrolytic cap by each FET’s drain pin and adding the RC snubber. *the furthest switch node has the worst ringing and is the furthest away from where power and ground leads come in from the battery

Guys I have good news! I’ve managed to reduce the ringing/spikes to manageable levels. I’ve added 4.7uF electrolytic caps by each FET as well as an RC snubber to each switch node. Between those two things, I only have a 15.4V spike when supplying the controller with 13.8V. I’m using a 4.7nF WIMA polypropylene cap and a 4.1ohm resistor for the RC snubbers.

I’ve added these extra caps and RC snubber to the PCB design for the future version. I suspect that capacitor value will not need to be as large since I’m pretty sure I’ve reduced the parasitic inductance in the layout/routing. Now I think I can move on to loaded testing!

9 Likes

This is amazing.

What does the spike measure at 50.4V supply voltage?

2 Likes